The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device capable of performing a clock alignment training especially to output internal data at a predetermined timing regardless of variations of process, voltage, and temperature (PVT), and a method for operating the semiconductor memory device.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a memory control unit (MCU), or stores data received from the data processor into memory cells selected by the addresses.
As the operating speed of the system is increasing and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed.
To meet this requirement, a synchronous semiconductor memory device was developed. The synchronous memory device is designed to input and output data in synchronization with a system clock. While the synchronous memory device inputs or outputs at one edge of the system clock, e.g., a rising edge, a double data rate (DDR) synchronous semiconductor memory device, which can input or output at falling edges and rising edges of the system clock, was developed, in order to increase a data input/output speed.
The DDR synchronous semiconductor memory device must be able to process two data during one cycle of the system clock so as to input or output data at a falling edge and a rising edge of the system clock. Specifically, the DDR synchronous semiconductor memory device should receive or output data exactly in synchronization with the rising edge and the falling edge of the system clock in order to perform data input/output operations without error.
To this end, a data output circuit is provided in the DDR synchronous semiconductor memory to control a timing of transferring and outputting internal data such that data is output in synchronization with rising and falling edges of the system clock.
However, even the DDR synchronous semiconductor memory device cannot meet the requirement of recent systems for inputting/outputting mass amounts of data at high speed. Therefore, recently, methods for increasing the speed of inputting/outputting addresses and thus increasing the speed of inputting/outputting data are being developed widely.
For example, in a typical DDR synchronous semiconductor memory device, the addresses are, together with an operation command, input in synchronization with a rising edge of a system clock. However, in a recently developed high-speed semiconductor memory device, the addresses are input in synchronization with a rising edge and a falling edge of the system clock, respectively.
In other words, the typical DDR synchronous semiconductor memory device receives one address and one operation command—i.e., corresponding to a rising edge of a system clock—from the outside in each cycle of the system clock to perform an internal operation. However, the recently developed high-speed semiconductor memory device receives two addresses—i.e., corresponding to the rising edge and the falling edge, respectively—and one operation command from the outside in each cycle of the system clock to perform an internal operation.
Therefore, the high-speed semiconductor memory device is being designed to receive addresses in synchronization with a falling edge as well as a rising edge of a system clock inputted from the outside. Consequently, the high-speed semiconductor memory device may have the following characteristics.
First, because the high-speed semiconductor memory device can receive two addresses in one cycle of the system clock, it is possible to reduce the number of pins for receiving addresses by half in comparison to the typical DDR synchronous semiconductor memory device.
Second, the extra pins which can be reduced as described above can be used for receiving a power supply voltage VDD or a ground voltage VSS. Accordingly, it is possible to stably supply the power supply voltage VDD and the ground voltage VSS, and thus increase the operation speed.
Third, the high-speed semiconductor memory device can receive two times more addresses than the typical DDR synchronous semiconductor memory device and the same number of operation commands as the typical DDR synchronous semiconductor memory device in each cycle of the system clock. Accordingly, the high-speed semiconductor memory device can control two times more memory capacity than the typical DDR synchronous semiconductor memory device with the same number of operation commands.
Further, the recently developed high-speed semiconductor memory device may have higher speed of inputting/outputting data than the typical DDR synchronous semiconductor memory device.
That is, whereas the typical DDR synchronous semiconductor memory device inputs/outputs data twice—i.e., corresponding to a rising edge and a falling edge of the system clock, respectively—in one cycle of the system clock, the high-speed semiconductor memory device can input/output data four times—twice corresponding to the rising edge, and twice corresponding to the falling edge—in one cycle of the system clock.
In summary, the high-speed semiconductor memory device is designed to input/output two data between a rising edge and a falling edge of the system clock, and input/output two data between the falling edge and the next rising edge. That is, four data are input/output in one cycle of the system clock.
However, since the system clock has only two logic states, a logic high state and a logic low state, in order to input/output four data in one cycle, a data clock having a frequency two times higher than the system clock is required. That is, a special clock for inputting/outputting data is additionally required.
Therefore, the high-speed semiconductor memory device inputs/outputs an address and a command based on the system clock while inputting/outputting data based on the data clock. Here, the data clock has two times higher frequency than the system clock.
In other words, two cycles of data clock run in one cycle of system clock, and the data is input/output at a rising edge and a falling edge of the data clock, respectively. Consequently, four data can be input/output in one cycle of the system clock.
As described above, contrary to the typical DDR synchronous semiconductor memory device performing a read or a write operation based on a single clock (a system clock), the high-speed semiconductor memory device performs a read or a write operation based on two clocks of different frequencies.
However, if the phases of the system clock and the data clock are not aligned, then the basis for transferring an operation command and an address and the basis for transferring data cannot be aligned either. This also means that the high-speed semiconductor memory device cannot operate normally.
Therefore, in order that the high-speed semiconductor memory device can operate normally, an interface training should be performed between a semiconductor memory device and a data processor in an early stage of the operation.
The interface training is a process for training the semiconductor memory device and the data processor so that they operate at a timing when an interface for transferring commands, addresses, and data is optimized, before the normal operation of the semiconductor memory device and the data processor.
Such an interface training includes an address training, a clock alignment training (WCK2CK training), a read training, a write training, and the like. The clock alignment training performs an operation for aligning a data clock and a system clock.